Process variations in integrated circuit fabrication cause variances in component dimensions, such as resistor width or transistor gate length, that affect circuit performance.
The specific problem to which the invention is applicable is the on-chip detection of these fabrication processing variances so as to enable integrated circuit designers to implement compensation schemes and thereby reduce the effect of variance on circuit performance
Most integrated circuits are designed using matched components to minimize the effects of process variability. Nevertheless, using conventional photolithographic techniques, significant process variance cannot be avoided. For example, process variances occur in photoresist procedures (including exposure time and developing), implant procedures and etching procedures, resulting in variations in the dimensions of the various deposited, implanted or etched regions that form the integrated circuits.
Moreover, these dimensional variances are not random, but rather occur in process steps that affect numerous components in the same way. That is, weak processing conditions will result in resistor widths that are generally less than nominal and gate lengths are generally greater than nominal, while strong processing conditions have just the opposite general effect. As a consequence, overall integrated circuit performance is affected.
Some processing variances are more critical to integrated circuit performance than others. For example, the most significant impact on performance in the case of bipolar processing is attributable to variations in resistor widths, and in the case of MOSFET processing is attributable to variations in gate lengths.
Specifically, bipolar delay and power are functions of resistor values, which are a function of resistor width. Similarly, MOSFET delay, edge rate, and power are a function of gate length. Using conventional photolithographic fabrication processes, for typical component sizes with nominal resistor widths of 3 microns or nominal gate lengths of 0.8 microns, resistor widths and gate lengths will generally exhibit variances in the range of 15-20% based on variations in resistor widths in the range of 0.4-0.5 microns and variations in gate lengths in the range of 0.15 microns.
The most common technique for reducing process variances is to increase nominal component size, so that a given dimensional variation is less of a percentage of nominal, and therefore, has less impact on component performance. Stated another way, a common result of process variances is that component sizes cannot be reduced below a minimum that is set by performance considerations attributable to processing variances rather than fabrication processing technology. This design constraint is disadvantageous in that it increases the chip area that must be allocated to those components that are significantly affected by process variances, and may even adversely affect performance of the integrated circuit.
The impact of process variances can be somewhat alleviated by focusing on those components and associated circuitry in which variations from design specifications are most detrimental. That is, component size can be increased for those circuits, such as regulators, oscillators, and other high speed logic, where performance output is particularly critical. For example, in the case of an integrated circuit design in which nominal resistor widths for bipolar circuitry are 3 microns, selected circuits can be fabricated using 30 micron resistor widths to reduce the effects of process variations on integrated circuit performance.
Such an approach is disadvantageous in that, for many integrated circuit designs, a significant portion of the circuitry will have to be up-sized. Further, such an approach does not solve the problem of process variance constraints that restrict further technologically feasible down-sizing of integrated circuit components. Moreover, such an approach does not address the performance problems that can result from up-sizing selected components, such as increased parasitic capacitance.
Accordingly, a need exists for an integrated circuit design technique for detecting fabrication process variations, thereby enabling process variance compensation schemes to be implemented.